Semiconductor integrated circuit device and method of manufacturing the same, and method of manufacturing masks

ABSTRACT

In forming linear circuit patterns running in vertical and horizontal directions, phases are arranged such that phases between proximate opening patterns are reversed. Type A phase conflict patterns have the same phase and are proximate to each other. Type B phase conflict patterns have reverse phases and are brought into contact with each other. Patterns for resolving the phase conflicts are generated, and a phase mask having a conflict resolving pattern and a complementary phase mask for forming a design pattern complementary therewith are subjected to multiple exposures on a substrate. Circuit patterns having a very small pitch which have been regarded to be difficult to manufacture can be manufactured by the multiple exposure of at most two sheets of the phase-shifting masks and a semiconductor integrated circuit device can be manufactured at low cost by designing the circuit patterns in a short period of time.

TECHNICAL FIELD

The present invention relates to a semiconductor integrated circuitdevice of a semiconductor device particularly including a logicintegrated circuit or logic LSI or the like, a method of manufacturingthe same and a method of manufacturing a mask formed with a pattern usedtherefor.

BACKGROUND ART

High performance/sophisticated features of a semiconductor integratedcircuit are achieved by miniaturized formation/highly integratedformation of a circuit pattern. For example, in the case of logic LSI,speeding-up has been promoted by reducing a gate length of a transistorand sophisticated features has been achieved by increasing a circuitdensity per unit area. In accordance therewith, a pitch of arrangingwirings (interconnected) for connecting logic gates to each other hasrapidly been miniaturized. With regard to progress in the wiring pitch,although currently, a pitch of 0.8 through 0.4 μm is considered to beachieved by using a KrF excimer laser exposure apparatus, further, apitch of about 0.3 μm is considered to be achieved by using an ArFexcimer laser exposure apparatus, it is anticipated that a pitch smallerthan 0.3 μm is difficult to realize by a conventional reductionprojection exposure method using deep ultra violet light. Hence, as amethod of realizing a further smaller pattern, an electron beam writingmethod (or EB lithography), an X-ray exposure method (or proximity X-raylithography) or the like has been investigated. Meanwhile, as a methodof promoting resolution performance of an optical system withoutchanging the optical system, there is known a phase-shifting mask.According to the method, phase of light transmitting through a specificlight transmitting portion (also referred to as opening portion) on amask is controlled (normally, reversed by 180 degrees), by whichresolution of an optical system is significantly promoted in comparisonwith a case of using a conventional mask.

According to the phase shifting method, there is needed phasearrangement for determining at which portion of a circuit pattern thephase is reversed at a design stage. However, according to an actualcircuit pattern, some patterns in which phase arrangement is essentiallydifficult may be produced. For example, a case in which U-shape patternsor three light transmitting patterns (that is, opening patterns) arearranged at distances the most proximate to each other, correspondsthereto and this is referred to as phase conflict. Since the problem isdifficult to resolve, the phase-shifting mask has been applied and usedto restrict to a simple pattern of a memory cell of the memory LSI orthe like.

A method of avoiding the phase conflict even in the case of applying thephase-shifting mask to a complicated pattern has been reported by Oi etal. According thereto, a layout avoiding the phase conflict iscalculated by carrying out compaction after phase arrangement at asymbolic level.

Other method of resolving the phase conflict is based on a concept ofcarrying out multiple exposure of a plurality of masks including thephase-shifting mask on the same photoresist layer. The concept has beenpatented by the inventors in Japanese Patent No. 2650962 and No.2638561. Further, application of the concept to various circuit patternshas been reported. For example, an application for forming a gatepattern of a logic LSI has been filed for patent by Jinbo or Komatsu etal. (Japanese Patent Laid-Open No. Hei 5(1993)-204131, Japanese PatentLaid-Open No. Hei 6(1994)-67403). Further, a method of applying theconcept to a wiring has been filed by B. J. Lin et al. (Japanese PatentLaid-Open No. Hei 8 (1996)-227140). Further, an arbitrary patterngeneration algorithm by a phase-shifting mask using a phase retrievalmethod has been proposed by Y. C. Pati et al. (SPIE: Optical/LaserMicrolithography VII, SPIE Vol. 2197 (1994) pp.314-327).

However, the above-described electron beam writing method or X-rayexposure method poses the following problems. First, according to theelectron beam writing method, enormous time is taken for successivelywriting individual patterns. Hence, there is investigated a cellprojection method capable of transcribing all pattern of a certaindegree of a scale (for example, about 5 μm square), however, a kind of apattern which can be set is limited and therefore, the method is noteffective in a random wiring pattern of a logic LSI. Further, althoughthere has been investigated an SCALPEL method capable of carrying outscanning exposure of a large area mask, the throughput is greatlyreduced compared with that of the current exposure method.

Further, according to the X-ray exposure method, there poses a problemthat it is difficult to realize a mask having sufficient accuracy.

Meanwhile, there poses the following problems in various methods whichhave been proposed conventionally for applying the phase-shifting maskmethod to an actual complicated circuit pattern.

For example, according to the method of carrying out compaction afterphase arrangement at a symbolic level, a circuit dimension of theportion of producing the phase conflict is alleviated and therefore, themethod is essentially counter to miniaturization of circuit.

Meanwhile, a logic LSI in recent times exceeds a manually designablescale and almost all of logic LSI's are designed by using an automaticplace and route method. Therefore, it is necessary to generate aphase-shifting mask with respect to automatically generated enormouspattern data and it is nonrealistic to generate the phase-shifting maskmanually by trial and error.

However, in the method of dealing with a complicated pattern by usingmultiple exposure of a plurality of masks, for example, according toJapanese Patent Laid-Open No. Hei 5(1993)-204131 or Japanese PatenLaid-Open No. Hei 8 (1996)-227140, a rule for decomposing an originaldesign pattern into a plurality of masks is not generalized andtherefore, there poses a problem that it is difficult to deal withactual enormous LSI data.

Further, methods disclosed in Japanese Patent Laid-Open No. Hei5(1993)-204131 or Japanese Patent Laid-Open No. Hei 6(1994)-67403, arefor miniaturizing a gate of a transistor and there poses a problem thatit is difficult to reduce a wiring pitch by applying the methods to awiring pattern.

Meanwhile, according to the method of decomposing a pattern in verticaland horizontal directions disclosed in Japanese Paten Laid-Open No. Hei8(1996)-227140, it is difficult to correspond to an arbitrary pattern ina random wiring of a logic LSI. For example, when a circuit pattern 5shown in FIG. 29 is decomposed in vertical and horizontal directions,two sheets of masks V and H are formed as shown by FIGS. 30(a) and30(b), however, in this case, for example, phase conflict between twolight transmitting portions (opening portions) X1 and X2 in the mask His not resolved. In FIG. 30, numeral 1 designates a light blockingportion and numerals 2, 3 and 4 designate light transmitting portions(opening portions). According to the above-described publicly-knownexample, there is suggested a way of thinking that the lighttransmitting (opening) patterns X1 and X2 on the mask are furtherdistributed to two sheets of masks, however, in this case, X1 and X2constitute incoherent summation and therefore, it is difficult toclearly separate these. Further, since there is not given a generalguiding principle therefor, it is difficult to apply the way to a largescale LSI pattern including an enormous random patterns for which manualoperation is substantially impossible as described above.

Further, since a phase arranging method using the phase retrieval methodrequires an enormous amount of calculation and therefore, it isdifficult to carry out the processing on the large scale data in apractical time period, further, the generated mask pattern iscomplicated, there poses a problem that a limit or the like in actuallymanufacturing a mask is not necessarily taken into consideration.

Meanwhile, the inventors have presented a method of capable of applyingphase shift to an arbitrary pattern by a further general algorism inDigest of Technical Papers, 1999 Symposium on VLSI Technology (1999)pp.123-124, “Node connection/quantum mask—Path to below 0.3-μm pitch,proximity effect free random interconnect and memory patterning”.

According to the method described in the 1999 Symposium on VLSITechnology, three sheets or more of masks are required for forming awiring pattern and there poses a problem that the mask cost isincreased.

As described above, there has not been a general and low cost method formaking an alternating type phase shifting method applicable to a randomwiring pattern. Therefore, there pose problems, (1) miniaturizedformation of a circuit pattern of a logic LSI and a reduction in a chiparea are determined by a limit of a wiring pitch of optical lithographyusing a conventional mask, and (2) the electron beam writing methodhaving an extremely low throughput is obliged to use when a reduction inthe wiring pitch exceeding a limit of optical lithography using theconventional mask is intended to achieve.

It is an object of the invention to provide an improved method ofmanufacturing a semiconductor integrated circuit device capable offorming a very small circuit pattern by a combination of a projectionexposure method and a phase-shifting mask.

Thereby, a logic LSI such as a microcomputer which is random (irregular)and having an enormous amount of very small circuit patterns at low costand in a short period of time. That is, by manufacturing a logic LSIhaving a random wiring pattern constituted by a very small wiringpattern having a wiring interval equal to or smaller than 0.15 μm byusing optical lithography, which has been regarded to be difficultrealistically by the conventional optical lithography, high performanceformation and high function formation of a semiconductor integratedcircuit device can be achieved at low cost.

It is other object of the invention to provide a method of designing andmanufacturing a mask pattern in which an alternating phase shifting isapplicable to an arbitrary pattern by multiple exposure of at most twosheets of phase-shifting masks even in the case of a very small circuitpattern having random (irregular) and an enormous amount of wiringpatterns or the like of a logic LSI, at low cost and in a short periodof time.

DISCLOSURE OF INVENTION

A simple explanation will be given as follows of an outline of arepresentative aspect of the invention disclosed in the application.

The invention is carried out by analyzing characteristics of phaseconflicts caused by shapes, arrangements and the like of variouspatterns in forming phase-shifting masks for a very small circuitpattern.

That is, the invention is carried out by analyzing various circuitpatterns of logic LSI which has been regarded to be difficult to useconventional phase-shifting masks, analyzing characteristics of phaseconflicts of particularly proximate patterns having straight lines,ends, L-shape portions and T-shape portions (that is, straight lineportions running in parallel in vertical and horizontal directions,line-ends, corners and intersections or crossings) and rather utilizingthe characteristics.

For example, according to a method of manufacturing a semiconductorintegrated circuit device of the invention, in forming an openingpattern having a plurality of straight lines, ends and L-shape portionsor T-shape portions in a photoresist film provided at an upper portionof a semiconductor region, the opening pattern is formed by subjectingthe photoresist film to multiple projection exposure by using two sheetsof masks comprising a first mask having a first light transmittingportion corresponding to the ends and the L-shape portions or T-shapeportions of the pattern and a second mask having a second lighttransmitting portion corresponding to the straight lines.

Further, when the plural straight lines, ends and L-shape portions orT-shape portions of the opening pattern are arranged neighbouringly toother straight lines or ends at intervals equal to or smaller than 0.15μm, the first mask and the second mask are constituted by phase-shiftingmasks.

Further, according to other method of manufacturing a semiconductorintegrated circuit device of the invention, in forming a circuit patternrunning in vertical and horizontal directions in a photosensitivematerial provided at an upper portion of a semiconductor region, thecircuit pattern is formed by subjecting the photosensitive material tomultiple exposure by using a projection optical system by using a firstphase shifting mask having a light transmitting portion corresponding toboth of patterns running in parallel proximately to each other in avertical direction of the circuit pattern and patterns running inparallel proximately to each other in a horizontal direction and asecond phase-shifting mask having a light transmitting portioncorresponding to any of line-ends, corners or intersections of thecircuit pattern.

According to still other method of manufacturing a semiconductorintegrated circuit device of the invention, in forming a pattern on aphotosensitive substrate by subjecting the substrate to projectionexposure by using a mask having a circuit pattern, the photosensitivesubstrate is subjected to multiple projection exposure by using a firstphase-shifting mask including a first phase conflict resolving maskpattern for forming a mask light transmitting portion corresponding to apattern region for constituting a first possible phase conflict regionat a vicinity of a distal end portion of a line pattern having anadjacent pattern within a predetermined distance therefrom and a secondphase conflict resolving mask pattern for forming a mask lighttransmitting portion corresponding to a pattern region for constitutinga second possible phase conflict region at a vicinity of an intersectionof a line pattern extended in a vertical direction and a line patternextended in a horizontal direction, and a second phases shifting maskincluding a complimentary pattern for forming the predetermined circuitpattern by subjecting the photosensitive substrate to multiple exposurealong with the first and the second phase conflict resolving maskpatterns to thereby form a very small circuit pattern on thephotosensitive substrate.

Further specifically, by subjecting a photoresist film to multipleprojection exposure by the above-described masks by using KrF excimerlaser, logic LSI constituted by a very small pattern having an irregularpitch equal to or smaller than 0.3 μm (that is, pattern width is equalto or smaller than 0.15 μm and pattern interval is equal to or smallerthan 0.15 μm) which has been regarded to be difficult to manufacture,can be manufactured with excellent reproducibility by using theconventional projection exposure technology. Further, similarly, whenArF excimer laser or F2 laser is used as a light source, a very smallpattern respectively having a pitch of 0.23 μm or a pitch equal to orsmaller than 0.19 μm can be dealt with.

Further, according to the invention, the circuit pattern is a pattern ofa region corresponding to a light transmitting portion (referred to alsoas opening portion) on a mask, that is, an opening portion provided at,for example, a positive-tone photoresist film and actually signifies apattern of any of a conductor region, a semiconductor region, or anonconductive region other than the above-described region in planararrangement of wirings or the like in a semiconductor device. Which of aconductor region, a semiconductor region or a nonconductive region isspecified by a light transmitting region (that is, opening region,region for irradiating light to a photoresist film) of a mask, differsby whether a positive-tone resist is used or a negative tone resist isused in a pattern transcribing process, or whether a wiring pattern isformed by etching a wiring material in a wiring process, or a wiringmaterial is embedded in a trench pattern in an insulator film by usingwhat is called damascene process.

Furthermore, the two sheets of masks suitable for the invention aremanufactured by the following procedure. That is, (1) when the lighttransmitting patterns arranged in parallel are proximate to each othersuch that a distance therebetween is within a predetermined value,phases of the light transmitting patterns are set such that phases oflight projected between the two light transmitting patterns are reverseto each other, (2) in a plurality of the light transmitting patternsdesignated with phases thereby, when the light transmitting patternshaving a same phase to be separated from each other are proximate toeach other within the predetermined distance, proximate portions thereofand patterns at vicinities thereof are extracted and stored as firstphase conflict region information in the meantime, when patterns to beconsecutive are constituted by a plurality of the light transmittingpatterns having different phases, overlap portions or contact portionsof the plurality of light transmitting patterns having the differentphases and patterns at vicinities thereof are extracted and stored assecond phase conflict region information, (3) phase conflict resolvingpatterns for resolving phase conflicts are generated corresponding tocorresponding respective regions by using the first and the secondconflict region information, (4) complimentary patterns for forming thedesired circuit pattern by subjecting a single photosensitive substrateto multiple exposure along with the phase conflict resolving patterns,are generated, (5) a first phase-shifting mask including the phaseconflict resolving patterns and a second phase-shifting mask includingthe complimentary patterns are manufactured.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1(a) and 1(b) are plain views schematically showing a wiringpattern constituting an object to which the invention is applied, FIG. 2is a pattern plane view for explaining a problem of the invention and afirst principle of the invention, FIG. 3 is a pattern plane view forexplaining a problem of the invention and a second principle of theinvention, FIGS. 4(a), 4(b) and 4(c) are pattern plane views forexplaining still other problem and principle of the invention, FIG. 5 isa pattern plane view showing still other principle of the invention,FIG. 6 is a pattern plane view showing a case of applying the inventionto a complicated pattern, FIG. 7 is a plane view schematically showing acomplicated wiring pattern constituting an object to which the inventionis applied, FIG. 8 is a flowchart showing a procedure of a case ofapplying the invention to a general pattern, FIG. 9 is a schematic viewshowing an effect of a case of applying the invention to a generalpattern, FIGS. 10(a) and 10(b) are schematic views showing a problem ina case of applying the invention to a general pattern, FIG. 11 is aschematic view showing a resolution method in a case of applying theinvention to a general pattern, FIGS. 12(a) and 12(b) are schematicviews showing other problem in a case of applying the invention to ageneral pattern, FIGS. 13(a) and 13(b) are schematic views showing otherproblem in a case of applying the invention to a general pattern, FIGS.14(a), 14(b) and 14(c) are schematic views showing various examples ofpattern correcting means applicable to the invention, FIGS. 15(a), 15(b)and 15(c) are schematic views showing other various examples of patterncorrecting means applicable to the invention, FIG. 16 is a schematicview showing other problem in a case of applying the invention to ageneral pattern, FIG. 17 is a schematic view showing one resolutionmethod of other problem of the invention, FIGS. 18(a), 18(b) and 18(c)are schematic views showing other resolution method of other problem ofthe invention, FIG. 19 is a schematic view showing other problem and aresolution method thereof of the invention, FIG. 20 is a schematic viewshowing other problem and a resolution method thereof of the invention,FIG. 21 is a schematic view showing an example of other patterncorrecting means of the invention, FIGS. 22(a) through 22(f) aresectional views of essential portions of respective steps showing stepsof manufacturing a semiconductor integrated circuit device according toan embodiment of the invention, FIG. 23 is a characteristic view showingan example of an electrode wiring pattern characteristic according to anembodiment of the invention, FIGS. 24(a) and 24(b) are schematic viewsshowing an exposure apparatus according to other embodiment of theinvention, FIGS. 25(a) through 25(d) are sectional views of essentialportions of respective steps showing steps of manufacturing asemiconductor integrated circuit device according to an embodiment ofthe invention, FIG. 26 is a schematic view showing an example of apattern generating algorism according to the invention, FIG. 27 is aschematic view showing other example of a pattern generating algorismaccording to the invention, FIGS. 28(a) and 28(b) are plane views ofessential portions for explaining an effect at a logic gate circuitportion formed by the invention, FIG. 29 is a plane view of a schematicpattern for explaining a problem of a conventional method, and FIGS.30(a) and 30(b) are plane views of a schematic pattern showing theproblem of the conventional method.

BEST MODE FOR CARRYING OUT THE INVENTION

In the following explanation, for simplicity, as shown by FIG. 1(a),circuit patterns 6, 7 and the like are constituted by line segmentshaving a predetermined width connecting lattice points of apredetermined lattice (hereinafter, referred to as basic lattice). Theassumption is substantially proper in a case of a large scaleinterconnected (wiring) systems designed on the premise of using toolsfor automatic place and route. In this case, a minimum wiring pitch ofFIG. 1 is made to be equal to or larger than a resolution limit of aphase shift exposure method and equal to or smaller than a resolutionlimit (for example, equal to or smaller than 0.3 μm) of the conventionalexposure method. Further, a black circle portion 8 in FIG. 1(a)indicates a portion of the pattern connected to an object of a wiring orthe like (for example, electrode or via) therebelow at the portion.

In order to resolve to clearly separate adjacent wirings by projectionexposure, it is necessary to reverse phases of two patterns running inparallel at a minimum interval of 0.15 μm. Hence, first, assume thatpatterns are arranged with phases such that the phases of the patternsarranged along basically adjacent lattice lines are reverse to eachother. This is carried out by decomposing the basic lattice intolattices 0 having a phase of 0 and lattices π having a phase of πrespectively in vertical and horizontal directions as shown by FIG. 1(b)and arranging the phase 0 to a pattern corresponding to a line segmenton the lattice 0 having the phase 0 and the phase π to a patterncorresponding to a line segment on the lattice π having the phase π.Further, in FIG. 1(b), a region of a white matrix indicates a patternhaving the phase of 0 degree and a hatched region indicates a patternthe phase of which is shifted by 180 degrees (the same as follows).

However, when this is applied to a designed arbitrary pattern,naturally, phase conflict is caused at everywhere. The phase conflict isdefined such that (1) a plurality of patterns having the equal phase tobe present independently (to be separated from each other), areproximate to each other at a certain distance (in the case of FIG. 1,about twice as much as basic lattice period) or less, or (2) a patternhaving a phase 0 and a pattern having a phase π are brought into contactwith each other or overlap each other.

The former is referred to as phase conflict of type A and the latter isreferred to as phase conflict of type B. When the phase conflict of typeA is caused, two patterns which are to be separated inherently, areconnected. Meanwhile, when the phase conflict of type B is caused, twopatterns to be connected inherently are separated.

FIG. 1(b) shows examples of the two types of phase conflicts A and B.Further, typical examples of the respectives are shown at upper left ofFIG. 2 and upper left of FIG. 3. Here, take note to that the phaseconflicts are necessarily caused at lattice points, or ends or cornersof patterns, or intersections.

The phase conflict of type A is caused at a portion at which a distancebetween line segment 51 and line segment 52 present on a lattice havinga phase 0 (or a lattice having a phase π), is equal to a minimum latticeinterval of the original basic lattice (upper right of FIG. 2). That is,when the lattice points belonging to two independent patterns having thesame phase are adjacent to each other at the minimum lattice interval,the phase conflict of type A is caused between the two lattice points.It is known that the phenomenon is necessarily caused between a latticepoint at a terminal end of a line segment and other line segment or aterminal point of other line segment. When the phase conflict of type Ais caused, the two patterns 51 and 52 to be separated from each otherbetween the two points are connected.

To resolve the phase conflict of this type, basically, the originalpattern is decomposed into two sheets of mask patterns, as shown by amiddle stage and a lower stage of FIG. 2 indicated by arrows and the twomask patterns are subjected to multiple exposure to the same resistfilm. A first mask (middle stage of FIG. 2) is a phase-shifting maskforming patterns 53 and 54 at positions corresponding to two latticepoints and a second mask (lower stage of FIG. 2) is a phase-shiftingmask for forming other line portions 55, 56 and 57. According to thesecond mask, an interval between the two independent patterns 55 and 56having the same phase, is expanded to a distance capable of separatingand resolving the two patterns even with the same phase. Thereby, thephase conflict of type A is resolved. Further, although according to theexample, all of terminal points of wirings are uniformly constituted bythe separate mask, this is not necessarily needed but only terminalpoints of wirings causing the phase conflict of type A may be extractedto the separate mask.

Meanwhile, the phase conflict of type B is caused, when polygonal lines(L-shape or T-shape lines) 58 and 59 constituting a single continuousline, are present over a lattice having a phase 0 and a lattice having aphase π, at a portion (L-shape portion) intersecting a portion belongingto the lattice having the phase 0 and a portion belonging the latticehaving the phase π (upper right in FIG. 3). That is, the phase conflictof type B is caused at the portion of intersecting the line segment 59present on the lattice having the phase 0 and the line segment 58present on the lattice having the phase π. It is known that thephenomenon is necessarily caused at corners of polygonal lines (L-shapeportions) or intersections (T-shape portions) of vertical lines andhorizontal lines. When the phase conflict of the type is caused, the twopatterns to be connected inherently are separated at the lattice point.

Hence, in this case, the original pattern is decomposed into two sheetsof mask patterns, shown at the middle stage and the lower state of FIG.3 indicated by arrows and the two mask patterns are subjected tomultiplex exposure to the same resist film. A first mask (middle stageof FIG. 3) is formed with a pattern 60 at a position corresponding tothe intersection (L-shape portion or T-shape portion) and a second mask(lower stage of FIG. 3) is formed with other line portions 61 and 62.Thereby, the phase conflict of type B is resolved. With regard thereto,although all of intersections of vertical and horizontal patterns areuniformly extracted, the conflict of type B is automatically resolved,all the intersections are not necessarily needed to extract but onlyterminal points of wirings causing phase conflict of type B may beextracted to the separate mask.

A phase mask pattern placed at a pair of lattice points interposing theabove-described phase conflict in order to resolve the phase conflict oftype A, and a mask pattern arranged at a lattice point at a position ofthe above-described phase conflict in order to resolve the phaseconflict of type B, can be arranged on one sheet of the same mask. Thetwo mask patterns are present on lattice points of an original basiclattice and therefore, by arranging the phases in checkers or in a shapeof a checker flag, the phases can be arranged without the phaseconflicts.

As described above, by decomposing the basic lattice into 0 lattices andπ lattices and subjecting a first phase-shifting mask constitutingphases of 0 and π by portions excluding portions of the phase conflictsof type A and type B, that is, patterns of straight line portionsrunning in parallel in vertical and longitudinal directions onrespective lattices and a second phase-shifting mask for exposing theportions of the phase conflicts of type A and type B, to multipleexposure, a random pattern on the lattices can be formed by two sheetsof the masks.

As described above, a description has been given of a case in which acircuit pattern is a wiring having a constant width along predeterminedlattices and a terminal end thereof is disposed on a lattice point.However, from the view point of flexibility of design, it is desirablethat the restriction is more or less alleviated. For example, a boldwiring is needed for a wiring having a comparatively long distance withconcern of wiring resistance. Further, in the case of a wiring at aninner portion of a standard cell of a logic LSI or the like, contact ona gate electrode and contact on an active region on a substrate, areshifted from each other by a half of a basic pitch. Therefore, there isa case in which a pattern deviated from the basic lattice is preferred.Hence, an explanation will be given as follows of a case of wiringshaving various widths and a case in which a pattern is present among thebasic lattice. Also in these cases, it is comparatively easy to expandthe invention.

First, assume that a wiring 65 having different width is defined byembedding an interval between wirings having a minimum line width alongthe basic lattice by a wiring pattern as shown by FIG. 4(a). Further,vias or contacts for connecting upper and lower substrates (notillustrated) are assumed to be present on the basic lattice as aprinciple. These assumptions are proper in many cases in designing alarge scale wiring system on the premise of using tools for automaticplace and route.

When phase conflicts of type A and type B are extracted based on theabove-described definition for lattice points of the basic latticeincluded in a contour of the design pattern 65, as shown by FIG. 4(b),the phase conflict of type B is caused at everywhere among the latticesas indicated by numeral 69 along the wiring pattern. This is understoodfrom the fact that when the bold wiring 65 is not present, line segmentsalong adjacent lattice lines are to be separated and phases of the bothare necessarily reversed and therefore, the phase conflict between theline segments cannot be caused. However, as described above, since thephase conflict of type B is defined between a lattice point and alattice point, the phase conflict between a line and a line is newlydefined as shown by FIG. 4(c) and is referred to as phase conflict oftype C.

When adjacent lattice lines on the basic lattice belong to the samepattern, the phase conflict of type C is caused between two pieces ofthe lattice lines included in the pattern. The phase conflict of thistype is resolved by decomposing an original pattern (upper stage of FIG.5) into two sheets of mask patterns as shown by a middle stage and alower stage of FIG. 5 by arrow marks and subjecting the mask patterns tomultiple exposure to the same resist film. That is, a first mask (middlestage of FIG. 5) is formed with a pattern 66 corresponding to a portionof the phase conflict, that is, a portion interposed by two latticelines and a second mask (lower stage of FIG. 5) is formed withphase-shifting patterns 67 and 68 corresponding to portions of otherline. Thereby, the phase conflict of type C is resolved.

Further, the above-described portion is not necessarily needed to beinterposed by wirings having a minimum line width along the basiclattice but can be dealt with by applying the above-described methodeven in the case in which the above-described portion is brought intocontact therewith on one side thereof.

A pattern for resolving the phase conflict of type A or B and a patternfor resolving the phase conflict of type C can be arranged on one sheetof the same mask. However, whereas the pattern for resolving the phaseconflict of type A or B is arranged on the lattice point of the basiclattice, the pattern for resolving the phase conflict of type C isarranged between the lattices of the basic lattice in a shape of line.Therefore, some caution is required when these are arranged on one sheetof the same mask to thereby arrange phases.

For example, in a case of a mixed pattern of a bold wiring 70 andwirings 71 and 72 having a minimum width, a pattern for resolving thephase conflict of type A or B and a pattern for resolving the phaseconflict of type C are brought into contact with each other andtherefore, it is difficult to arrange phases.

In this case, in consideration of functions of the bold wiring andconnection points priority is given to resolution of the phase conflictof type A or B at a vicinity of a terminal end of a wiring and there maybe formed two sheets of masks of arrangements as shown at a middle stageand a lower stage of FIG. 6 indicated by arrows.

That is, as a pattern for resolving the phase conflict of type C, theremay be used a feature contracting a pattern of the bold line portion 70respectively by about one side W (=half of basic period) in a wiringwidth direction and about one side 2W in a wiring longitudinaldirection.

Thereby, at a distal end portion (front end portion, terminal endportion), the phase conflict of type A or B is resolved and connectionwith other wiring or via or the like can firmly be carried out,meanwhile, at portions other than the distal end, by resolving the phaseconflict of type C, the bold wiring can be realized to thereby reducewiring resistance.

Next, a description will be given of a case of applying the invention toa pattern of a further general arrangement in which a pattern is presentalso among the basic lattice. First, there is defined a sub-lattice at aposition shifted from the basic lattice by a half period respectively invertical and horizontal directions.

Assume that a design pattern is constituted by a combination (sumregion) of line segments having a width W (=half of basic period) on thebasic lattice and line segments having a width W on the sub-lattice asshown by FIG. 7. FIG. 8 shows a total flow of processings in this case.

First, features of a bold pattern 73 are extracted from a patternfirstly constituting an object and a pattern for resolving the conflictof type C is generated based on the above-described method. Next, whenthe above-described pattern of resolving the conflict of type C isexcluded from the original pattern, there remain patterns having aminimum line width on the basic lattice and the sub-lattice.

When the sub-lattice is divided into lattices 0′ and lattices π′ similarto the pattern on the basic lattice, the above-described pattern belongsto any one of lattices 0, lattices π, lattices 0′ and lattices π′.Therefore, by forcibly arranging phases in accordance with theabove-described lattices, both of the phase conflicts of type A and typeB can be caused respectively between patterns belonging to the basiclattice, patterns belonging to the sub-lattice and between patternsbelonging to the basic lattice and patterns belonging to thesub-lattice. Hence, phase conflicts of type A and type B are extractedand there are generated conflict resolving patterns with regard to theseconflicts based on the above-described method. The conflict resolvingpatterns are removed from the original pattern as necessary and this isdefined as a first phase mask. Further, conflict resolving patterns oftypes A, B and C are arranged on one sheet of the same mask and definedas a second phase mask. A description will be given as follows of amethod of arranging phases in the respective masks. Although it ispreferable to apply pertinent optical proximity effect correction (OPC)for individual pattern shapes on the respective masks, a descriptionwill later be given with regard thereto. First, according to the firstphase mask, as shown by FIG. 9, whereas a minimum line interval betweenpatterns on the basic lattice and patterns on the sub-lattice, is a halfW of the basic pitch, a distance between a pattern on the basic latticeand a pattern on the sub-lattice independent from each other, is atleast equal to or larger than twice (2W) of the minimum interval.

Although according to the invention, W is defined to be about a minimumresolvable dimension of phase shifting at minimum, in this case,patterns having an interval therebetween separated by about 2W canalways be separated without depending on a phase relationship of both.Therefore, a pattern on the basic lattice and a pattern on thesub-lattice pose no problem when the patterns are arranged on one sheetof the same mask. That is, line patterns excluding phase conflictportions on the respective lattices can be arranged on one sheet of thesame first phase mask. The phase of the respective pattern can bedetermined by, for example, on which of lattice 0, lattice π, lattice 0′and lattice π′ the individual pattern is present. Next, consider variouskinds of patterns for resolving phase conflicts (pattern features) inthe above-described second phase mask. The conflict of type A can becaused any of between lattice points having the same phase of the basiclattice, between lattice points having the same phase of the sub-latticeand between a lattice point of the basic lattice and a lattice point ofthe sub-lattice having a phase the same as a phase of the lattice pointof the basic lattice. When these are classified respectively as typesA-1, A-2 and A-3, although a minimum distance between conflicts of thesame type is equal to a minimum resolvable dimension of phase shifting,there is a possibility that a distance between conflict resolvingpatterns of different types becomes 0 as shown by FIG. 10(a).

In this case, it is necessary to arrange phases of the conflictresolving mask such that phases of conflict resolving patterns incontact with each other are equal to each other as shown by, forexample, FIG. 10(b). This is carried out by setting phases on theconflict resolving masks corresponding to lattice points havingdifferent phases of vertical and horizontal lines, become always equalto each other regardless of the basic lattice or the sub-lattice asshown by FIG. 11.

Thereby, even when A-1 and A-3 are brought into contact with each otheras shown by FIG. 10, the phases of the conflict resolving patterns incontact with each other can be made equal to each other. In view ofrespectives of lattice points of the basic lattice, lattice points ofthe sub-lattice, intersections of vertical basic lattice and horizontalsub-lattice and intersections of horizontal basic lattice and verticalsub-lattice, phases are arranged in a shape of a checker flag and aminimum distance thereof is equal to the minimum resolvable dimension ofphase shifting. Therefore, conflict resolving patterns at other thanportions in contact with each other can always be separated andresolved.

Also phase conflict of type B can be defined and resolved quite similarto a case of only the basic lattice. That is, regardless of the basiclattice or the sub-lattice, intersections of patterns of phase 0 andphase π constitute the phase conflict of type B. Among them, phaseconflicts on the basic lattice or phase conflicts on the sub-lattice arearranged at the period of the basic lattice, there is a possibility thata minimum distance of conflict between the basic lattice and thesub-lattice and between the same lattices becomes 0 and the conflictsare brought into contact with each other (FIG. 12(a)). In this case, itis necessary to arrange phases of a conflict resolving mask as shown byFIG. 12(b) such that phases of the conflict resolving patterns incontact with each other become equal. This can be carried out by settingphases on the conflict resolving mask as shown by FIG. 11 quite similarto that for the above-described conflict of type A.

FIG. 13 shows an example of an exceptional case of causing phaseconflict between phase resolving patterns by the phase arranging methodshown in FIG. 11. According to patterns shown in FIG. 13(a), conflictresolving patterns are present at three lattice points consecutive inone direction on the basic lattice. According to phase arrangement insuch a case, it is preferable to make all of phases of the threeconsecutive phase conflict resolving patterns equal to each other asshown by FIG. 13(b) without depending on the method of FIG. 11.

Although geometrical processings in this case are complicated, in manycases, such a complicated wiring pattern is a wiring at inside of alogical cell and therefore, the problem may be dealt with by extractingconflicts in designing the cell and correcting the design individually.When the inter-cell wirings are mixed, it is preferable to arrangephases on a premise of connecting the wirings to terminals in the cell.All of the above-described operation can be formed into a rule by thegeometrical operation and accordingly, operation can automatically becarried out by what is called automatic geometrical operation tool. FIG.26 shows an example of a basic algorism. A specific program will laterbe given by embodiments. Further, for simplification, in FIG. 26, a boldline pattern and a pattern between the basic lattice are omitted.

That is, as shown by an arrow mark on the right side of an originaldesigned pattern shown at top left of FIG. 26, lateral lines areextracted and phase arrangement with regard thereto is set andhorizontal lines are extracted and phase arrangement with regard theretois set. Successively, as shown by arrow marks therebelow, intersectionsof phases 0/π are extracted and the above-described portions of phaseconflict of type B are extracted and 0 phase patterns and phase πpatterns are collected to thereby extract the above-described portionsof phase conflict of type A. Based on the result, patterns for resolvingrespective phase conflicts are generated and as shown by an arrow mark,and patterns for resolving phase conflicts are collected. Further, afirst mask P for resolving phase conflicts is formed by allocatingproper phase arrangement to the collected patterns for resolving phaseconflicts and further, a second mask Q for forming line pattern featuresis formed by subtracting the collected patterns for resolving phaseconflicts from the collected pattern of the horizontal and laterallines.

Further, in order to simplify generation of remaining pattern data otherthan predetermined pattern by subtracting predetermined pattern datafrom original pattern data, the operation is referred to as generatingcomplimentary patterns.

Meanwhile, according to the first phase mask, there are generatedpatterns of various shapes from a square shape to line and spacepatterns. It is generally difficult as miniaturization is progressed toform the various patterns simultaneously and accurately. In order toresolve this, it is preferable to carry out optical proximity effectcorrection (OPC). FIG. 14 shows an example of OPC applicable to theinvention.

FIG. 14(a) shows an example of OPC with regard to a pattern on a maskfor a line pattern. A thin line 80 in the drawing shows an originaldesign pattern and a bold line 81 shows a shape of a pattern aftercorrection. For example, it is preferable that a line width of anisolated pattern having a large distance to an adjacent pattern, is madebolder than a line width of a crowded pattern having a comparativelysmall distance and a line width of a line pattern having a short lengthand a dimension of a very small pattern in a square shape is relativelymade large. Although according to the invention, it is necessarilyneeded to add a very small correction pattern of what is called hammerhead, serif or the like to an individual pattern on a mask, even whenthe very small correction pattern is added, no trouble is brought about.

FIGS. 14(b) and 14(c) show an example of OPC with regard to patterns onthe above-described mask for resolving conflicts. Although the patternfor resolving conflicts is basically a very small pattern in a squareshape, it is preferable to pertinently change a size and a shape thereofin accordance with the type of phase conflict, a distance to an adjacentpattern or the like as shown by a bold line 84. Particularly, a patternfor resolving phase conflict of type B is for connecting two throughfour pieces of patterns to each other and therefore, it is effective tocorrect the pattern in accordance with the object such as constitutingvarious shapes as shown by bold lines 85 of FIG. 14(c).

Further, when the pattern for resolving conflicts are present toisolate, in order prevent projected images thereof from being widened tosurroundings, a peripheral node pattern 86 as shown by FIG. 15(a) may beadded. When no problem is guaranteed in view of circuit function, theperipheral node patterns 86 may be arranged at regions where patternsare not present in view of design.

Further, with regard to a very small pattern in a square shapeoriginally present on a designed pattern, a very small square dummypattern 87 may previously be arranged on a lattice point of a portionwhere wiring patterns are not present at a surrounding thereof (FIG.15(b)). Phase arrangement of the dummy pattern 87 may be carried out inaccordance with phases of lattices.

Although the peripheral node patterns 86 or the dummy patterns 87 may beresolved by themselves, there can be constituted a very small auxiliarypattern 88 which cannot be resolved by itself as shown by FIG. 15(c). Aposition of the auxiliary pattern 88 in this case is not necessarilyneeded to dispose on an adjacent lattice point but it is preferable topertinently optimize a distance from a center of a phase conflictresolving pattern and a shape thereof.

By adding the various OPC methods explained above, accuracy of afinished pattern and honesty for a designed pattern can further bepromoted.

Further, in the case in which other phase conflict resolving pattern orperipheral node pattern is arranged at a position of a lattice pointadjacent to a phase conflict resolving pattern of type B as shown atupper left of FIG. 16, when a photoresist film is subjected toprojection exposure by using two masks of a mask for line patternfeatures and a mask for patterns to resolve phase conflicts as shown bya second stage of FIG. 16 by arrow marks, as shown by a lowermost stageof FIG. 16 by an arrow mark, there is a concern of causing constrictions89 and 90 at the pattern of the finished photoresist film. This isbecause whereas according to a projected image formed by the mask forpatterns to resolve phase conflicts, as shown by the second stage and athird stage of FIG. 16, the optical intensity becomes 0 at positions ofdotted lines 91 and 92, according to the mask for line pattern features,as shown by dotted lines 93 and 94 in the drawing, the optical intensitybecomes 0 at middles of vertical and horizontal lines phases of whichare reverse, that is, on skewed 45 degree lines of intersections andpositions of the two masks where the optical intensity becomes 0, areproximate to each other, or at a position where the optical intensitybecomes 0 at one of the masks, the optical intensity of an image ofother mask is not sufficient provided.

When the constriction pattern poses a problem, as shown by FIG. 17, itis conceivable that pattern arrangement per se of an original pattern 95at upper left of FIG. 17 is changed as shown by upper right thereof (96)and two sheets of masks of a mask 97 for line pattern features and amask 98 for patterns to resolve phase conflicts are formed as shown at alower stage of FIG. 17 by arrow marks. Such a measure can be carried outwhen patterns are designed manually as in wirings at inside of a cell.

However, when the change is carried out by returning to a designedpattern, the change is troublesome from the view point of design flow,which may not necessarily be preferable.

Hence, in this case, the pattern to resolve phase conflicts of type Bmay be improved as shown by FIG. 18. Further, in FIGS. 18(a), 18(b) and18(c), a mask 99 for line pattern features is shown on the left side anda mask 100 for patterns to resolve phase conflicts is shown on the rightside. FIG. 18(a) shows decomposition of mask patterns before theimprovement and FIGS. 18(b) and 18(c) show a result of decomposing maskpatterns after improvement.

First, according to an improvement method shown in FIG. 18(b), actualphase conflict is shifted not to an intersection (or corner) of lattice0 and lattice π but onto a lattice point at a position shifted from acorner by one period of the basic lattice. Thereby, the problem as shownby FIG. 16 can be resolved.

Further, according to an improvement method show by FIG. 18(c), when aT-shape intersection is arranged on a plurality of consecutive latticepoints, these are dealt with as a feature having the same phase. Apattern for resolving phase conflicts is set to a lattice point on anouter side of a lattice point on an outer side of the consecutivelattice points. The method may be carried out only when horizontal lineportions of characters of T (heads) of consecutive T-shapeintersections, are aligned on a straight line as shown by FIG. 18(c).When the restriction is not carried out, there is a concern of causingphase conflicts among the line patterns and therefore, caution isrequired.

By further generalizing the improvement method shown by FIG. 18(b) asfollows, processings can be automated. According to the method describedabove (refer to FIG. 3), the phase conflict of type B is resolved byconstituting only an intersection causing the conflict by separate mask.However, a pattern for resolving phase conflict of type B is not limitedto the pattern shown in FIG. 3 but FIG. 3 only shows the simplest ofconceivable conflict resolving patterns. Hence, in this case, there isutilized other pattern for resolving the phase conflict of type B.Basically, a predetermined range centering on a pattern intersectioncausing a phase conflict of type B, is replaced by a predeterminedconflict resolving pattern. In this case, the above-described conflictresolving pattern can be constituted by a combination of patterns on afirst mask and patterns on a second mask.

FIG. 19 shows an example of a pattern for resolving conflict of type Band a method of generating the pattern. A pattern at inside of a squareshape 106 written by a thin line at a topmost stage of FIG. 19 centeringon a portion of phase conflict of type B, is replaced by a pattern forresolving phase conflict generated by the following procedure as shownby arrow marks in the drawing.

First, a pattern 103 for resolving phase conflict of type B on a maskfor resolving phase conflict is constituted by calculating a commonregion of a pattern 101 and a designed pattern 102 and pertinentlycorrecting a shape thereof. Further, a pattern 105 for resolving phaseconflict of type B on a mask for forming line portion features, isconstituted by calculating a common region of a pattern 104 and adesigned pattern 102 and pertinently correcting a shape thereof. Thepatterns for resolving phase conflicts of type B on the respectivemasks, are fitted to inside of a square shape written by a thin line andmade to merge to patterns on an outer side thereof. Phases of thepatterns for resolving phase conflicts of type B on the mask forresolving phase conflicts can be determined based on coordinates oflattice points at which respective patterns are placed.

Although any phases will do for the pattern 105 for resolving phaseconflicts on the mask for forming line portion features, the phases canbe determined, for example, based on, coordinates of lattice pointscausing the phase conflicts.

According to the method, an opening pattern is necessarily generated ata lattice adjacent to the portion of conflict of type B on the mask forresolving phase conflict and therefore, even when other phase conflictis present neighbourly to the above-described conflict of type B, theother phase conflict can be resolved without problem.

Similarly, FIG. 20 shows other pattern of resolving phase conflicts anda procedure of generating the pattern. According to the method of FIG.20, by directly connecting patterns of the same phase on an inner sideand an outer side of a thin line 206 on a mask for forming the lineportion features, an amount of pattern data can be restrained. Further,the above-described pattern of FIG. 18(c) is provided by applying themethod shown in FIG. 20.

Further, also with regard to the method shown in FIG. 18(c) the methodcan be generalized as follows. A proximate pattern of T-shape crossingshorizontal line portions of which are aligned and adjacent to a straightline, is extracted and allocated with phases as a single aggregation.The phases can be determined by, for example, from phases of lattices atthe horizontal line portions aligned on the straight line. Next, thepattern is collected to other portion of a circuit pattern subjected tophase arrangement forcibly. As a result of collecting, new phaseconflict is caused between a portion allocated with the phases as thesingle aggregation and other portions and therefore, the conflictresolving pattern may be generated at contact portions.

According to the above-described explanation, it is assumed that all thepatterns excluding the inner portion of the bold line, is firstlysubjected to phase arrangement forcibly. However, actually, the phasearrangement may be limited to a minimum necessary range. This isachieved by, for example, a method shown in FIG. 27.

First, there are extracted characteristics of line-ends, corners,intersections and the like from an original designed pattern at leftupper of FIG. 27. Further, patterns proximate to each other within acertain distance are extracted and vicinities thereof are made toconstitute a phase shifting applying region. Further, whereas phasearrangement is carried out for the phase shifting applying region inaccordance with the procedure shown by FIG. 8, FIG. 26, FIG. 18 or thelike, with regard to patterns other than the phase shifting applyingregion, for example, phase 0 degree is allocated. Thereafter, patternsat inside of the phase shifting applying region and at outside of theregion respectively allocated with phases, are collected. As a result ofcollecting, phase conflicts are caused and therefore, the phaseconflicts are extracted and patterns for resolving phase conflicts aregenerated. Caution is particularly required in dealing with contactpoints of a pattern having phase π at inside of the phase shiftingapplying region and a pattern at outside of the phase shifting applyingregion allocated with phase 0 degree, as new phase conflict of type B.In this way, there are formed two sheets of masks of a first mask P forresolving phase conflicts and a second mask Q for forming line patternfeatures.

By minimizing the phase-shifting region in this way, yield ofmanufacturing masks can be promoted by restraining a density of defectsof, for example, the phase-shifting mask. This is because when, forexample, an engraving portion of a phase mask is constituted by a regionof phase π, by minimizing an area of the engraving region, a number ofdefects in etching the substrate in the region can be restrained.

Further, according to the invention, a resolving pattern may begenerated by extracting only minimum necessary portions or a resolvingpattern may be generated by extracting all of portions which may causeconflicts. For example, in the case of a pattern 111 shown at an upperstage of FIG. 21, when a conflict resolving pattern is generated byextracting only conflict portions, the original pattern 111 isdecomposed into two sheets of masks 112 and 113 as shown by lower leftof FIG. 21 by arrow marks. In this case, a proximity effect correctionof adding a hammer head or the like as shown in the drawing can also becarried out for a pattern having a reverse phase caused on the secondmask.

Meanwhile, conflict resolving patterns are generated for all the lineends which may cause conflicts and decomposed into masks, at two sheetsof masks 114 and 115 shown at lower right of FIG. 21 by other arrowmarks on the right side. Also in this case, in accordance with a phaserelationship between patterns opposed on the second mask, there may becarried out a correction of changing pattern dimensions and patternpositions on the first mask.

(Embodiment 1)

An explanation will be given as follows of an example of forming adamascene wiring pattern layer pattern having a pitch of 0.3 μm byapplying the above-explained method.

First, with regard to the designed wiring layer pattern having the pitchof 0.3 μm, in accordance with the method explained in reference to FIG.26, mask data for two sheets of phase masks, that is, mask data forresolving phase conflicts and mask data for forming line patternfeatures are formed. In pattern data processings therefor there are usedtools for geometrical operation for processing what is called mask data.Used programs are shown below.

Further, when dimensions, pitches and the like of wiring patterns arechanged, it is preferable to pertinently change various dimensionparameters in the programs, further, when function with regard toprograms are substantially equivalent, the programs are not limited tothe above-described.

In the following programs, SIZE(A;d), XSIZE(A;d), YSIZE(A;d)respectively designate operations moving respective sides of a pattern Afrom an inner side to an outer side of the pattern A in all directions,x direction, y direction by d and AND, +, − designate geometricalBloolean operation. Notation input designates geometrical data oforiginal designed pattern and notation Res_mask designates geometricaldata of opening patterns of a mask for resolving phase conflicts andnotation Line_mask designates geometrical data of opening patterns of amask for forming line pattern features. Notation w designates a wiringwidth of a wiring pattern which is equal to a half of a period of abasic lattice. Notations dA, dB, dP respectively designate patterns forresolving phase conflicts of type A and type B and a dimension or shapecorrection parameter of a peripheral node pattern. Further, notation dLEdesignates a parameter for designating an amount of regress of a lineend in contact with phase conflict of type A on a mask for forming linepattern features. Further, a portion surrounded by “” in the programsindicates a sentence of comment.

“Extract and Classify Line, Line-Crossing, Line-End”

input: “original mask data”

HS=XSIZE (input;−w)

HL=XSIZE (Hs;w): “horizontal lines”

VS=YSIZE (input;−w)

VL=YSIZE(VS;w): “vertical lines”

H_(—)0=AND (HL, H_(—)0 degree): “horizontal lines with 0 degree”

HL_p=AND (HL, H_p degree): “horizontal lines with p degree”

VL_(—)0=AND (VL, V_(—)0 degree): “vertical lines with 0 degree”

VL_p=AND (VL, V_p degree): “vertical lines with p degree)”

LN_(—)0=HL_(—)0+VL_(—)0: “lines with 0 degree”

LN_p=HL_p+VL_p: “lines with p degree”

X_(—)00=AND (HL_(—)0, VL_(—)0): “cross point of 0 degree H-line and 0degree V-line”

X_pp=AND (HL_p, VL_p): “cross point of p degree H-line and p degreeV-line”

X_(—)0p=AND (HL_(—)0, VL_P) “cross point of 0 degree H-line and p degreeV-line”

X_p0=AND (HL_P, VL_(—)0): “cross point of 0 degree H-line and p degreeV-line”

X=X_(—)00+X_pp+X_(—)0p+X_p0: “cross point”

LE=(HL−HS)+(VL−VS)−X: “line end”

“Extract Type-A & Type-B Phase-Conflict”

typeA_(—)0=XSIZE(XSIZE(LN_(—)0;w/2);−w/2)+YSIZE(YSIZE(LN_(—)0;w/2);−w/2)−LN_(—)0

typeA_p=XSIZE(XSIZE(LN_p;w/2);−w/2)+YSIZE(YSIZE(LN_p,w/2);−w/2)−LN_p

typeA=typeA_(—)0+typeA_p: “type A phase conflict”

Res_A=AND ((XSIZE(typeA; W)+YSIZE(typeA; w)), LE)

typeB=X_(—)0p+X_p0: “type B phase conflict”

Res_B=tepeB

“Extract Peripheral Node”:

Node=Res_A+Res_B

P_node1=AND(XSIZE(Node;2w)+YSIZE(Node;2w)−SIZE (Node;w), input):“possible peripheral node”

A=XSIZE (Node;w)+YSIZE (Node;w) B=SIZE (AND (A, input)−Node; w)

C=SIZE (A−B; w)

D=AND (B−C, PND1): “unnecessary peripheral node”

P_node=P_node1−D: “peripheral node”

“Patterns for Phase Conflict Resolution Mask”:

Res_mask=SIZE(Res_A; dA)+AND(SIZE (Res_B;dB), input)+SIZE(P_node;dP)

“Patterns for Line Mask”:

Line_mask=XSIZE(HL;−dLE)+YSIZE(VL;−dLE)+X_(—)00+X_pp+(LE-Res_A)−Res_B

By the above-described program, only portions of causing phase conflictsof type A and type B on designed data are extracted and patterns forresolving these are generated on the mask for resolving phase conflicts.Further, the above-described program shows only portions of generatingopening pattern data on the respective masks. Further, actually withregard to the patterns generated above, there are carried out proximityeffect correction and phase arrangement in accordance with positions onlattices (a specific program will be omitted here). Based on the maskdata generated in this way, two sheets of phase-shifting masks areformed. There are used structures of the phase-shifting masks similar tothose which have been known generally.

Next, an explanation will be given of steps of forming a wiring patternusing the above-described mask in reference to FIG. 22. First, an Sioxide film 12 is deposited on aa predetermined LSI substrate (Si) 11 tobe formed with the damascene wirings thereabove. A predeterminedanti-reflection coating 13 is formed thereabove and a positive tonephotoresist film 14 for KrF excimer laser is coated to form (FIG.22(a)).

Next, the mask 1A for resolving phase conflicts is exposed afteraligning an alignment mark attached to a side of a substrate (wafer)with an alignment mark attached to the mask 1A as explained in the nextembodiment 2 (FIG. 22(b)). In exposure, there is used a reductionprojection exposure apparatus (not illustrated) having a numeralaperture of 0.6 and constituting a light source by KrF excimer laser.

Successively, exposure is carried out by changing the mask 1A forresolving phase conflicts to the mask 1B for forming line patternfeatures and overlapping the same position on the same resist film 14(FIG. 22(c)). At this occasion, in order to remove an error caused by alimit of reproducibility of detecting the alignment mark attached to theside of the substrate, two sheets of the masks are subjected to multipleexposure while fixing the wafer on a wafer stage. An explanation will begiven of details thereof in Embodiment 2. FIG. 23 shows atwo-dimensional (planar) distribution of a total sum of an amount ofexposure of light irradiated into the photoresist film 14 by themultiple exposure. A photo-chemical reaction is caused in the resist inaccordance with the amount of irradiating light, thereby, solubility ofthe resist is changed. It is known that the soluble reaction is causedin the resist substantially by a shape of the designed pattern. Next,after carrying out multiple exposure by two sheets of the masks, apredetermined heat treatment is carried out and the resist film isdeveloped, as a result, the resist film is removed from a portion 15 tobe formed with a desired wiring pattern (FIG. 22(d)).

Next, by using a formed resist pattern 16 as a mask of etching, theanti-reflection coating 13 and the oxide film 12 are selectively etchedto remove and thereafter, the resist 16 and the anti-reflection coating13 are removed and a trench (opening portion) 17 of the oxide film isformed at a portion to be formed with the desired wiring pattern (FIG.22(e)).

Thereafter, a barrier metal and a metal film of copper or the like aredeposited in the trench (opening portion) of the oxide film and on theoxide film 12 as a wiring material, further, the metal film on the oxidefilm 12 is removed by subjecting a surface thereof to chemicalmechanical polishing (CMP) to thereby leave the metal film only atinside of the trench (opening portion) to thereby form a desired wiringpattern 18 (FIG. 22(f)).

By the embodiment, a random wiring pattern having a very small pitchwhich has been difficult to resolve conventionally by theabove-described exposure apparatus, can be formed with high accuracy andhigh yield. Further, mask pattern data used therefor can be designed inshort period.

The wiring pattern, the kind of the exposure apparatus, wavelength ofexposed light, the resist process, the wiring forming process and thelike are not limited to those described in the embodiment. For example,an A1 wiring pattern may be formed by using an i-line reductionprojection exposure apparatus, forming a hard mask and ananti-reflection coating on an A1 film, coating a negative tone resistthereon, subjecting two sheets of masks to multiple exposure anddevelopment and etching a matrix with the provided resist pattern as amask. Further, an order of exposure of two sheets of the masks may bechanged. After exposing the first mask by aligning the first mask to thealignment mark on the wafer, the second mask may be exposed by aligningthe second mask again to the above-described alignment mark.

(Embodiment 2)

According to the embodiment, an explanation will be given of theexposure apparatus used in the above-described embodiment and anexposure sequence in reference to FIG. 24.

First, after fixing a substrate wafer 21 to a wafer adsorbing base on awafer stage 22, an alignment mark 23 on the substrate is detected and adetection signal (wafer mark signal) thereof is stored to a pertinentstorage medium. Meanwhile, a first mask 24 is fixed to a mask mountingstage (not illustrated) and an alignment mark 25 on the first mask 24 isdetected. Next, by using the wafer mark signal 23 and the detectionsignal of the alignment mark 25 on the first mask 24, the first mask 25and the substrate 21 are accurately aligned and thereafter, the firstmask 24 is exposed to a resist mask (not illustrated) on the substrate21 via a projection lens 26 (FIG. 24(a)). As the exposure apparatus, KrFexcimer laser apparatus is used similar to the above-described.

Next, while fixing the substrate waver 21 at the wafer adsorbing base,the first mask 24 is changed to a second mask 27, thereafter, the secondmask 27 and the substrate 21 are accurately aligned by using the wafermark signal 23 and a detection signal of an alignment mark 28 on thesecond mask 27 and thereafter, the second mask 27 is exposed to theresist film on the substrate 21 (FIG. 24(b)).

Thereby, a factor of alignment error of patterns exposed by therespective masks, is constituted only by an error caused by a limit ofreproducibility of detecting the alignment marks on the masks andpositional accuracies of the patterns on the masks and 20 nm is achievedas alignment accuracy between the first mask and the second mask. By theembodiment, the random wiring pattern having the very small pitch can beformed by making high alignment accuracy and high throughput compatibleto each other.

Although according to the embodiment, exposure is carried out by usingthe exposure apparatus of what is called stepper type for carrying outthe exposure in a state in which the masks and the substrate arestationary, there may be used an exposure apparatus of what is calledscan type for exposing the both while relatively scanning the both.Further, the effect of the invention is effective without depending onthe light source of the exposure apparatus, a type of a projectionoptical system or the like.

Further, when a chip size on the mask is smaller than a half of aneffective exposure region of the exposure apparatus, by arranging toalign the pattern on the first mask (first pattern) and the pattern onthe second mask (second pattern) on one sheet of the mask substrate, thealignment accuracy can further be promoted and the mask cost cansignificantly be saved.

According to an exposure method in this case, a second pattern region onthe mask is blocked by using the masking blade function of the exposureapparatus, only the first pattern is exposed to a predetermined position(normally, plural positions) on the wafer substrate, successively,without removing the wafer from the wafer adsorbing base, the firstpattern region is blocked by the masking blade and only the secondpattern is exposed onto the wafer substrate. At this occasion, withregard to the above-described respective predetermined positions,exposure is carried out by moving the wafer stage from the position ofexposing the first pattern by an amount of offset corresponding to adistance between an original point of the first pattern and an originalpoint of the second pattern on the masks above the wafer substrate.However, in the multiple exposure, the original points of the tworegions are to coincide with each other. In this case, the throughput ishalved in comparison with the case of arranging a pattern for two chipson one sheet of a reticule.

Further, the throughput can also be prevented from being lowered bycarrying out the operation as follows.

First, the first pattern region and the second pattern region aresummarizingly exposed to a predetermined position on the substrate.Next, the first pattern region and the second pattern region aresummarizingly exposed again after moving the wafer stage by the amountof offset corresponding to the distance between the original point ofthe first pattern region and the original point of the second patternregion on the masks above the wafer substrate.

Thereby, the first exposure region in exposure at a second time canoverlappingly be transcribed to the second pattern region transcribed byexposure at a first time. By repeating the procedure, without using themasking blade function, the first pattern region and the second patternregion can be subjected to multiple exposure over an entire face of thewafer.

In this case, the first pattern and the second pattern are exposed underthe same exposure condition and therefore, it is preferable topertinently adjust pattern dimensions on the masks of the respectivepattern regions such that patterns can be transcribed under the sameexposure condition.

The above-described procedure is applicable not only to a reductionprojection exposure apparatus of step and repeat system but also to areduction projection exposure apparatus of what is called step and scansystem similar to the above-described case.

(Embodiment 3)

In this embodiment, an explanation will be given of a method ofmanufacturing a semiconductor integrated circuit device using the methodof Embodiment 1 in reference to FIG. 25.

FIG. 25 is a schematic view showing a manufacturing process of theabove-described semiconductor apparatus by using a sectional view of atypical portion of the device.

First, an isolation region 32 comprising an insulating substance of SiO₂or the like is formed in an Si substrate 31 (FIG. 25(a)), thereafter, aplurality of semiconductor regions for constituting a plurality of MOStransistors 33 are formed (FIG. 25(b)) and contact holes 34 are formed(FIG. 25(c)). Numeral 41 designates an insulating film of SiO₂ or thelike. Thereafter, first layer wirings 35 and an inter-wiring insulatingfilm 36 are formed (FIG. 25(c)), an inter-layer insulating film 37 andconductive vias or contacts 38 embedded therein are formed thereaboveand a second layer wiring 39 and an inter-wiring insulating film 40 areformed (FIG. 25(d)).

Wirings of a third and further wirings (not illustrated) are similarlyformed. According to the embodiment, in forming patterns of the firstlayer wiring and the second layer wiring, a method similar to that shownin Embodiment 1 is used.

By the embodiment, a semiconductor integrated circuit having very smallpitch wirings which have been difficult to manufacture by theconventional projection exposure method, can be manufactured with highaccuracy, high yield and high throughput.

(Embodiment 4)

According to the program of Embodiment 1, only portions of causing thephase conflicts of type A and type B are extracted in view of designdata and patterns for resolving the phase conflicts are generated on thephase conflict resolving mask. Therefore, a number of patterns forresolving the phase conflicts are generated on the phase conflictresolving mask. Therefore, a number of patterns for the phase conflictresolving mask is restrained and burden with regard to writing the maskcan be reduced. However, on the other hand, the geometrical operation israther complicated and therefore, in the case of the large scalesemiconductor circuits, there poses a problem that time is required ingenerating pattern data in the respective mask.

Hence, according to the embodiment, all of wiring ends which may causethe phase conflict of type A are extracted, patterns on the phaseconflict resolving mask are generated therefor, further, also withregard to type B, all of intersections and corners of vertical andhorizontal patterns which can cause the phase conflict of type B areextracted and patterns on the phase conflict resolving mask aregenerated therefor. Individual phase arrangement in the mask forresolving the phase conflicts of the both types and the mask forstraight line portions, is carried out after generating all the patterndata for two sheets of the masks. Also according to the embodiment, byapplying the embodiment to the lock LSI, the mask data can be generatedin a comparatively short period of time.

(Embodiment 5)

Next, an explanation will be given of an example of applying theinvention to an NAND cell as an actual logic gate circuit portion.

FIG. 28 shows a planar pattern of the NAND cell per se and FIG. 28(a)shows a constitution manufactured by using the conventional projectionexposure technology without applying the invention and isolationregions, source regions, drain regions, gate electrodes and the like areformed at a pitch of 0.5 μm, that is, at intervals of 0.25 μm.

In contrast thereto, as a result of tentatively manufacturing an NANDgate circuit cell having a pattern constitution quite the same as thatof FIG. 28(a) by using an exposure apparatus the same as that explainedin reference to FIG. 24, as shown by FIG. 28(b), isolation regions,source regions, drain regions, gate electrodes and the like can beformed at a pitch of 0.3 μm, that is, at intervals of 0.15 μm and it canbe confirmed that an area reducing effect for a semiconductor chip issignificant.

Further, it can also be confirmed that by changing the exposureapparatus or the resist process used, the size of the mask pattern canfurther be reduced. Thereby, there can be achieved a prospect of capableof manufacturing LSI by freely using the projection exposure technologyeven in the case of a very small pattern having an interval smaller thana pitch of 0.3 μm, that is, smaller than 0.15 μm. For example, it isconfirmed that a main pattern design dimension can be reduced by about10% by changing the numeral aperture of the KrF excimer laser exposureapparatus from 0.6 to 0.68 and a pattern dimension can be reduced byabout 20% by using the ArF excimer laser exposure apparatus.

As described above, as is understood from the various explanation, theinvention is applicable to forming the isolation region 32, or the gateelectrode pattern and the source and the drain electrode patterns of theMOS transistor 33, and/or forming electrode wirings 34 and the like atan inner portion of a very small circuit unit constituted thereby, bysubstantially similar procedures. Further, the invention is applicablenot only to forming the electrodes and the wiring patterns but alsoapplicable to forming very small patterns for selectively forming anumber of semiconductor regions constituting a number of circuitelements at inside of a semiconductor substrate of Si or the like.

INDUSTRIAL APPLICABILITY

As described above, according to the invention, in forming random(irregular) and an enormous amount of very small circuit patterns, bysubjecting at most two sheets of phase-shifting masks of a phase maskarranged with phases such that phases between opening patterns proximateto each other corresponding to a circuit pattern are reversed and havinga phase conflict resolving pattern generated for the phase conflict oftype A in which same phase patterns are proximate to each other and thephase conflict of type B in which reverse phase patterns are broughtinto contact with each other, and a complimentary phase mask for forminga design pattern complimentarily therewith, to multiple exposure on thesame substrate, even when a dimension of the circuit pattern exceeds aresolution limit of the conventional light exposure method, the circuitpattern can be formed. Thereby, a semiconductor circuit (particularly,logic LSI having a random wiring pattern) having a very small wiringpattern which has been considered to be difficult to manufacturerealistically by the conventional optical lithography, can bemanufactured by using the optical lithography and high performanceformation and high function formation of a semiconductor apparatus canbe achieved at low cost. Further, even a random (irregular) and anenormous amount of very small circuit patterns of a wiring pattern of alogic LSI or the like having a very small circuit dimension exceeding aresolution limit of the conventional light exposure method, can bedesigned and manufactured at low cost and in a short period of time.

What is claimed is:
 1. A method of manufacturing a semiconductor integrated circuit device characterized in that in forming a pattern on a photosensitive substrate by subjecting the substrate to projection exposure by using a mask having a circuit pattern, the photosensitive substrate is subjected to multiple projection exposures by using: a first phase-shifting mask including: a first phase conflict resolving mask pattern for forming a mask light transmitting portion corresponding to a pattern region for constituting a first possible phase conflict region at a vicinity of a distal end portion of a linear aperture having an adjacent pattern of the same phase arranged in a light shielding area within a predetermined distance therefrom, and a second phase conflict resolving mask pattern for forming a mask light transmitting portion corresponding to a pattern region for constituting a second possible phase conflict region at a vicinity of an intersection of a linear aperture extending in a vertical direction and a linear aperture extending in a horizontal direction having different phases, respectively; and a second phase-shifting mask including a linear aperture complementary pattern for forming the predetermined circuit pattern by subjecting the photosensitive substrate to multiple exposures along with the first and the second phase conflict resolving mask patterns.
 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, characterized in that the circuit pattern is present on a predetermined lattice and the first and the second phase conflict resolving mask patterns are present on lattice points of the lattice.
 3. A method of manufacturing a mask characterized in that, in manufacturing a mask for forming a circuit pattern on a substrate by projecting a mask constituting a light transmitting pattern by the circuit pattern to a resist film formed on the substrate by way of a projection optical system: a pattern at a vicinity of a distal end portion of a linear aperture pattern having an adjacent pattern of the same phase arranged in a light shielding area within a predetermined distance therefrom is extracted and stored as first possible phase conflict region information, a pattern at a vicinity of an intersection of a linear aperture pattern extended in a vertical direction and a linear aperture pattern extended in a horizontal direction having different phases, respectively, is extracted and stored as second possible phase conflict region information, phase conflict resolving patterns for resolving phase conflicts are generated corresponding to respective regions by using the first and the second phase conflict region information, linear aperture complementary patterns for forming the desired circuit pattern by subjecting a same photosensitive substrate to multiple exposures along with the phase conflict resolving patterns are generated, and a first phase-shifting mask including the phase conflict resolving patterns and a second phase-shifting mask including the linear aperture complementary patterns are manufactured.
 4. The method of manufacturing a mask according to claim 3, characterized in that the phase conflict resolving pattern for the first possible phase conflict region is a phase-shifting pattern arranging phases reverse to each other to a pair of regions interposing a space region at distal end portions of line patterns.
 5. The method of manufacturing a mask according to claim 4, characterized in that the phase conflict resolving pattern for the second possible phase conflict region includes a light transmitting portion arranged at an intersection of the line patterns.
 6. The method of manufacturing a mask according to claim 5, characterized in that the circuit pattern is present on a predetermined lattice and the phase conflict resolving-patterns are present on lattice points of the lattice.
 7. The method of manufacturing a mask according to claim 4, characterized in that the circuit pattern is present on a predetermined lattice and the phase conflict resolving patterns are present on lattice points of the lattice.
 8. The method of manufacturing a mask according to claim 3, characterized in that the circuit pattern is present on a predetermined lattice and the first and the second phase conflict resolving patterns are present on lattice points of the lattice. 